TSMC's technology roadmap; Intel cuts; reciprocal hacking; McKinsey on IC challenges, ML algorithm table; subsystem chiplets; ...

A NoC provides a structured and scalable approach to transporting data between the growing number of IP blocks in a chip.

EDA vendors are taking aim at new ways to improve the productivity of design and verification engineers, who are struggling ...

Complexity, uncertainty, and lots of moving pieces will challenge the semiconductor industry for years to come.

EDA software is revolutionizing high-speed digital design by accelerating time-to-market despite growing complexity.

Moving data through a chip or package, and between packages and systems, is becoming a much bigger challenge as the volume of data continues to explode, and as more compute resources are deployed to ...

It is easy to blame it all on the leading-edge designs. They get all the attention. But there just aren’t enough of them to ...

While analog and digital verification efforts have been essentially separated, closer integration is resulting in a ...

Capturing a granular view of link operation using specialized data packets designed to carry debug information.

Predictive modeling, strategic sampling and embedded monitors help accelerate testing for yield limiting defects.

Early verification of symmetry and IP placement with pattern matching technology has a profound impact on IC design ...

A new technical paper titled “Hardware-based Heterogeneous Memory Management for Large Language Model Inference” was ...